Field of the Invention
The invention relates to a bipolar memory cell with random access, comprising an upper word line, a lower word line, two bit lines, two transistors each having two emitters, a base and a collector fed back crosswise to the base, two Schottky diodes, two low-resistance load resistors each forming a series circuit with a respective one of the Schottky diodes, two high-resistance load resistors each forming a parallel circuit with a respective of of the series circuits, each of the parallel circuits being connected between a respective one of the collectors and the upper word line, one of the emitters of each of the transistors being connected to the lower word line, and the other of the emitters of each of the transistors being connected to a respective one of the bit lines.
Such a memory cell for a static bipolar memory with random access is known from a paper by Masaaki Inadachi et al entitled: A 6 ns 4 Kb Bipolar RAM Using Switched Load Resistor Memory Cell, IEEE-ISSCC 1979, page 108 et seq. The principle behind such a memory cell is that one of the two-emitter transistors is always conducting and the other is always cut off. To this end, the collectors of the transistors are fed back crosswise to the bases and connected through the respective parallel circuit of a high-resistance load resistor and a Schottky diode in series with a low-resistance load resistor to an upper word line, while one emitter of each transistor is tied to a common lower word line and the other emitter of each transistor is connected to a bit line.
A bipolar memory contains a multiplicity of such memory cells disposed in the form of a matrix. The row selection is accomplished through the upper word line, the potential of which is raised or lowered. The potential of the lower word line follows the upper word line. The column selection is accomplished by the two bit lines and the determination as to which of the transistors conducts and which does not.
In stand-by operation, the high-resistance load resistor of the conducting transistor is effective since the upper word line and the bit lines are not selected. If a cell is selected, on one hand the upper word line is raised with respect to its potential and on the other hand the bit lines are connected to a current source. In this way, a current flows through the Schottky diodes and the low-resistance load resistor, so that the resulting total load resistance of the conducting transistor assumes a low resistance. When selecting the memory cell, the current is about 2 to 3 orders of magnitude larger than the standby current.
When information is stored, the process is reversed, so that one transistor is switched into the conducting state quickly and the other is switched into the cut-off state relatively slowly. The low-resistance load resistor in connection with the storage capacitance, provides the required storage excursion of about 400 to 500 mV.
In bipolar memories according to the state of the art, the capacitances which serve in principle for the storage of electric charges for the information storage in a semiconductor memory, are formed by the base-collector and the Schottky diode capacitance, the value of which is about 400 fF. This relatively large capacitance requires large specific capacitances and large areas for the Schottky diode and the base of the transistors. It is a disadvantage in such a case that the capacitance of the pn junction depends on the voltage and that the active area of the components is larger than is required due to design rules and emitter areas, which results in a large collector-substrate capacity. Furthermore, a large specific base-collector capacitance increases the typical time constants which have a detrimental effect in logic applications.
On the other hand. the collector-substrate capacitance of a bipolar memory cell should be as small as possible for reasons of interferrence suppression, since in rewriting, the collector-substrate capacitance must reverse the charge polarity and thus counteract the charging of the storage capacitance. According to experience, the ratio of the effective storage capacitance to the parasitic collector-substrate capacitance is to be larger than 5.
It is accordingly an object of the invention to provide a bipolar memory cell with an external capacitance, which overcomes the hereinfore-mentioned disadvantages of the heretoforeknown devices of this general type, to improve the speed of the logic and interference suppression of a bipolar storage cell and to offer the possibility of optimizing and constructing the cell components separately.